Philips Semiconductors
Product specification
Remote 8-bit I/O expander for I
2
C-bus
6
CHARACTERISTICS OF THE I
2
C-BUS
6.2
Start and stop conditions
PCF8574
The I
2
C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer
may be initiated only when the bus is not busy.
6.1
Bit transfer
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the stop condition (P) (see Fig.5).
6.3
System configuration
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this
time will be interpreted as control signals (see Fig.4).
A device generating a message is a ‘transmitter’, a device
receiving is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are
controlled by the master are the ‘slaves’ (see Fig.6).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.4 Bit transfer.
SDA
SDA
SCL
S
START condition
P
STOP condition
SCL
MBC622
Fig.5 Definition of start and stop conditions.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
MBA605
SLAVE
RECEIVER
MASTER
TRANSMITTER
Fig.6 System configuration.
1997 Apr 02
6
PHILIPS [ NXP SEMICONDUCTORS ]
