NXP Semiconductors
PCF8574; PCF8574A
Remote 8-bit I/O expander for I
2
C-bus with interrupt
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I
2
C-BUS
MULTIPLEXER
SLAVE
002aaa966
Fig 13. System configuration
9.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit (see
The acknowledge bit is an active LOW level (generated
by the receiving device) that indicates to the transmitter that the data transfer was
successful.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that wants to issue an
acknowledge bit has to pull down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of the acknowledge bit related
clock pulse; set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by
not
generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
S
START
condition
1
2
8
clock pulse for
acknowledgement
002aaa987
9
Fig 14. Acknowledgement on the I
2
C-bus
PCF8574_PCF8574A
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 27 May 2013
12 of 33
PHILIPS [ NXP SEMICONDUCTORS ]
