PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF8566 are timed by the frequency
fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency
fclk(ext)
.
The clock frequency (fclk) determines the LCD frame frequency (ffr) and the maximum rate
for data reception from the I2C-bus. To allow I2C-bus transmissions at their maximum data
rate of 100 kHz, fclk should be chosen to be above 125 kHz.
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the
output from pin CLK is the clock signal for any cascaded PCF8566s or PCF8576s in the
system.
7.5.2 External clock
Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the
external clock input.
Remark: A clock signal must always be supplied to the device. Removing the clock,
freezes the LCD in a DC state.
7.6 Timing
The timing of the PCF8566 sequences the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between the PCF8566s in the system. The timing also generates the LCD
frame frequency which is derived as an integer division of the clock frequency (see
Table 6). The frame frequency is set by the mode set commands when an internal clock is
used or by the frequency applied to the pin CLK when an external clock is used.
Table 6.
LCD frame frequencies [1]
PCF8566 mode
Frame frequency
Nominal frame frequency (Hz)
normal mode
69 [2]
f clk
f fr
=
=
------------
2880
power saving mode
65 [3]
f clk
f fr
---------
480
[1] The possible values for fclk see Table 20.
[2] For fclk = 200 kHz.
[3] For fclk = 31 kHz.
The ratio between the clock frequency and the LCD frame frequency depends on the
mode in which the device is operating. In the power-saving mode the reduction ratio is six
times smaller; this allows the clock frequency to be reduced by a factor of six. The
reduced clock frequency results in a significant reduction in power dissipation.
PCF8566_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2009
15 of 48
NXP [ NXP ]
