Philips Semiconductors
PCF8563
Real-time clock/calendar
handbook, full pagewidth
500 ns
2000 ns
SDA
SCL
8 ms
power up
override active
MGM664
Fig 5. POR override sequence.
8.9 Serial interface
The serial interface of the PCF8563 is the I
2
C-bus. A detailed description of the
I
2
C-bus specification, including applications, is given in the brochure:
The I
2
C-bus
and how to use it,
order no. 9398 393 40011 or
I
2
C Peripherals Data Handbook IC12.
8.9.1
Characteristics of the I
2
C-bus
The I
2
C-bus is for bidirectional, two-line communication between different ICs or
modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor. Data transfer may
be initiated only when the bus is not busy.
The I
2
C-bus system configuration is shown in
Figure 6.
A device generating a
message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device
that controls the message is the ‘master’ and the devices which are controlled by the
master are the ‘slaves’.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
MBA605
SLAVE
RECEIVER
MASTER
TRANSMITTER
Fig 6. I
2
C-bus system configuration.
8.9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the start condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the
stop condition (P); see
Figure 7.
width
SDA
SDA
SCL
S
START condition
P
STOP condition
SCL
MBC622
Fig 7. START and STOP conditions on the I
2
C-bus.
9397 750 04855
© Philips Electronics N.V. 1999. All rights reserved.
Product specification
16 April 1999
13 of 30
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