Philips Semiconductors
PCF8563
Real-time clock/calendar
8.7 EXT_CLK test mode
A test mode is available which allows for on-board testing. In this mode it is possible
to set up test conditions and control the operation of the RTC.
The test mode is entered by setting bit TEST1 in the Control/Status1 register. The
CLKOUT pin then becomes an input. The test mode replaces the internal 64 Hz
signal with the signal that is applied to the CLKOUT pin. Every 64 positive edges
applied to CLKOUT will then generate an increment of one second.
The signal applied to the CLKOUT pin should have a minimum pulse width of 300 ns
and a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from
CLKOUT, is divided down to 1 Hz by a 2
6
divide chain called a pre-scaler. The
pre-scaler can be set into a known state by using the STOP bit. When the STOP bit is
set, the pre-scaler is reset to 0. STOP must be cleared before the pre-scaler can
operate again. From a STOP condition, the first 1 s increment will take place after
32 positive edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 s
increment.
Remark:
Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz
clock. When entering the test mode, no assumption as to the state of the pre-scaler
can be made.
8.7.1 Operation example
1. Enter the EXT_CLK test mode; set bit 7 of Control/Status 1 register (TEST = 1)
2. Set bit 5 of Control/Status 1 register (STOP = 1)
3. Clear bit 5 of Control/Status 1 register (STOP = 0)
4. Set time registers (Seconds, Minutes, Hours, Days, Weekdays, Months/Century
and Years) to desired value
5. Apply 32 clock pulses to CLKOUT
6. Read time registers to see the first change
7. Apply 64 clock pulses to CLKOUT
8. Read time registers to see the second change.
Repeat steps 7 and 8 for additional increments.
8.8 Power-On Reset (POR) override mode
The POR duration is directly related to the crystal oscillator start-up time. Due to the
long start-up times experienced by these types of circuits, a mechanism has been
built in to disable the POR and hence speed up on-board test of the device. The
setting of this mode requires that the I
2
C-bus pins, SDA and SCL, be toggled in a
specific order as shown in
Figure 5.
All timing values are required minimum.
Once the override mode has been entered, the chip immediately stops being reset
and normal operation starts i.e. entry into the EXT_CLK test mode via I
2
C-bus
access. The override mode is cleared by writing a logic 0 to bit TESTC. Re-entry into
the override mode is only possible after TESTC is set to logic 1. Setting TESTC to
logic 0 during normal operation has no effect except to prevent entry into the POR
override mode.
9397 750 04855
© Philips Electronics N.V. 1999. All rights reserved.
Product specification
16 April 1999
12 of 30
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