NXP Semiconductors
PCF8563
Real-time clock/calendar
8.3 Control registers
8.3.1 Register Control_status_1
Table 5.
Bit
7
Control_status_1 - control and status register 1 (address 00h) bit description
Symbol
TEST1
Value
0
[1]
1
6
5
N
STOP
0
[2]
0
[1]
1
4
3
N
TESTC
0
[2]
0
1
[1]
2 to 0
[1]
[2]
Description
normal mode
must be set to logic 0 during normal operations
EXT_CLK test mode
unused
RTC source clock runs
all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC
clock is stopped (CLKOUT at 32.768 kHz is still available)
unused
Power-On Reset (POR) override facility is disabled; set to logic 0 for
normal operation
Power-On Reset (POR) override may be enabled
unused
Reference
Section 8.9
Section 8.10
Section 8.11.1
N
000
[2]
Default value.
Bits labeled as N should always be written with logic 0.
8.3.2 Register Control_status_2
Table 6.
Bit
7 to 5
4
N
TI_TP
Control_status_2 - control and status register 2 (address 01h) bit description
Symbol
Value
000
[1]
0
[2]
1
Description
unused
INT is active when TF is active (subject to the status of TIE)
INT pulses active according to
Table 7
Remark:
note that if AF and AIE are active then INT will be
permanently active
3
AF
0
[2]
1
2
TF
0
[2]
1
1
0
AIE
TIE
0
[2]
1
0
[2]
1
[1]
[2]
Reference
Section 8.3.2.1
and
Section 8.8
read: alarm flag inactive
write: alarm flag is cleared
read: alarm flag active
write: alarm flag remains unchanged
read: timer flag inactive
write: timer flag is cleared
read: timer flag active
write: timer flag remains unchanged
alarm interrupt disabled
alarm interrupt enabled
timer interrupt disabled
timer interrupt enabled
Section 8.3.2.1
Bits labeled as N should always be written with logic 0.
Default value.
PCF8563
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 3 April 2012
8 of 50
PHILIPS [ NXP SEMICONDUCTORS ]
