PCF8563
NXP Semiconductors
Real-time clock/calendar
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from master
SLAVE ADDRESS
DATA
S
0
A
REGISTER ADDRESS
A
S
1
A
A
SLAVE ADDRESS
n bytes
R/W
R/W
auto increment
memory register address
(1)
no acknowledgement
from master
1
P
DATA
last byte
auto increment
memory register address
013aaa041
(1) At this moment master transmitter becomes master receiver and PCF8563 slave receiver becomes slave transmitter.
Fig 20. Master reads after setting register address (write register address; READ data)
acknowledgement
from slave
acknowledgement
from master
no acknowledgement
from master
1
A
A
DATA
1
P
S
SLAVE ADDRESS
DATA
R/W
n bytes
last byte
auto increment
register address
auto increment
register address
013aaa347
Fig 21. Master reads slave immediately after first byte (READ mode)
PCF8563
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 3 April 2012
27 of 50
NXP [ NXP ]
