PCF8563
NXP Semiconductors
Real-time clock/calendar
Table 26. First increment of time circuits after STOP bit release
[1]
Bit
Prescaler bits
F0F1-F2 to F14
1 Hz tick
Time
Comment
STOP
hh:mm:ss
Clock is running normally
0
01-0 0001 1101 0100
12:45:12
prescaler counting normally
STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally
1
XX-0 0000 0000 0000
12:45:12
prescaler is reset; time circuits are frozen
New time is set by user
1
XX-0 0000 0000 0000
08:00:00
prescaler is reset; time circuits are frozen
STOP bit is released by user
0
XX-0 0000 0000 0000
XX-1 0000 0000 0000
XX-0 1000 0000 0000
XX-1 1000 0000 0000
:
08:00:00
08:00:00
08:00:00
08:00:00
:
prescaler is now running
-
-
-
:
11-1 1111 1111 1110
00-0 0000 0000 0001
10-0 0000 0000 0001
:
08:00:00
08:00:01
08:00:01
:
-
0 to 1 transition of F14 increments the time circuits
-
:
11-1 1111 1111 1111
00-0 0000 0000 0000
10-0 0000 0000 0000
:
08:00:01
08:00:01
08:00:01
:
-
-
-
:
11-1 1111 1111 1110
00-0 0000 0000 0001
08:00:01
08:00:02
-
0 to 1 transition of F14 increments the time circuits
013aaa076
[1] F0 is clocked at 32.768 kHz.
The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP
bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset
(see Table 26) and the unknown state of the 32 kHz clock.
PCF8563
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 3 April 2012
21 of 50
NXP [ NXP ]
