PCF8563
NXP Semiconductors
Real-time clock/calendar
8.9 EXT_CLK test mode
A test mode is available which allows for on-board testing. In such a mode it is possible to
set up test conditions and control the operation of the RTC.
The test mode is entered by setting bit TEST1 in register Control_status_1. Then
pin CLKOUT becomes an input. The test mode replaces the internal 64 Hz signal with the
signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then
generate an increment of one second.
The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a
maximum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is
divided down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set into
a known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0 (STOP
must be cleared before the prescaler can operate again).
From a STOP condition, the first 1 second increment will take place after 32 positive
edges on CLKOUT. Thereafter, every 64 positive edges will cause a one-second
increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.
When entering the test mode, no assumption as to the state of the prescaler can be made.
8.9.1 Operation example:
1. Set EXT_CLK test mode (Control_status_1, bit TEST1 = 1).
2. Set STOP (Control_status_1, bit STOP = 1).
3. Clear STOP (Control_status_1, bit STOP = 0).
4. Set time registers to desired value.
5. Apply 32 clock pulses to CLKOUT.
6. Read time registers to see the first change.
7. Apply 64 clock pulses to CLKOUT.
8. Read time registers to see the second change.
Repeat steps 7 and 8 for additional increments.
PCF8563
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 3 April 2012
19 of 50
NXP [ NXP ]
