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PCB80C552-5-16WP/07 参数 Datasheet PDF下载

PCB80C552-5-16WP/07图片预览
型号: PCB80C552-5-16WP/07
PDF下载: 下载PDF文件 查看货源
内容描述: IC- SM- CPU\n [IC-SM-CPU ]
分类和应用:
文件页数/大小: 24 页 / 187 K
品牌: NXP [ NXP ]
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Philips Semiconductors  
Product specification  
Single-chip 8-bit microcontroller  
80C552/83C552  
AC ELECTRICAL CHARACTERISTICS (Continued)  
SYMBOL  
PARAMETER  
INPUT  
OUTPUT  
2
I C Interface (Refer to Figure 9)  
1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
START condition hold time  
14 t  
> 4.0µs  
HD;STA  
LOW  
CLCL  
CLCL  
CLCL  
1
SCL low time  
16 t  
14 t  
> 4.7µs  
1
SCL high time  
> 4.0µs  
HIGH  
2
SCL rise time  
1µs  
RC  
3
SCL fall time  
0.3µs  
250ns  
250ns  
250ns  
0ns  
< 0.3µs  
FC  
Data set-up time  
> 20 t  
– t  
SU;DAT1  
SU;DAT2  
SU;DAT3  
HD;DAT  
SU;STA  
SU;STO  
BUF  
CLCL  
RD  
FC  
1
SDA set-up time (before rep. START cond.)  
SDA set-up time (before STOP cond.)  
Data hold time  
> 1µs  
> 8 t  
CLCL  
> 8 t  
– t  
CLCL  
1
Repeated START set-up time  
STOP condition set-up time  
Bus free time  
14 t  
14 t  
14 t  
> 4.7µs  
> 4.0µs  
> 4.7µs  
CLCL  
CLCL  
CLCL  
1
1
2
SDA rise time  
1µs  
0.3µs  
RD  
3
SDA fall time  
< 0.3µs  
FD  
NOTES:  
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.  
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1µs.  
3. Spikes on the SDA and SCL lines with a duration of less than 3 t  
SCL = 400pF.  
will be filtered out. Maximum capacitance on bus-lines SDA and  
CLCL  
4. t  
= 1/f  
= one oscillator clock period at pin XTAL1. For 62ns, 42ns, 33.3ns < t  
< 285ns (16MHz, 24MHz, 30MHz > f  
>
CLCL  
OSC  
CLCL  
OSC  
2
1.2MHz) the SI01 interface meets the I C-bus specification for bit-rates up to 100 kbit/s.  
15  
1998 Aug 13  
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