LPC2210/2220
NXP Semiconductors
16/32-bit ARM microcontrollers
Table 4.
Pin description …continued
Symbol
Pin (LQFP)
Pin (TFBGA) Type
Description
P1.26/RTCK
52[5]
N6[5]
I/O
RTCK — Returned Test Clock output. Extra signal added to
the JTAG port. Assists debugger synchronization when
processor frequency varies. Bidirectional pin with internal
pull-up.
Note: LOW on this pin while RESET is LOW, enables pins
P1[31:26] to operate as Debug port after reset.
P1.27/TDO
P1.28/TDI
P1.29/TCK
144[5]
140[5]
126[5]
B2[5]
A3[5]
A7[5]
O
I
TDO — Test Data out for JTAG interface.
TDI — Test Data in for JTAG interface.
I
TCK — Test Clock for JTAG interface. This clock must be
slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface
to operate.
P1.30/TMS
113[5]
43[5]
D10[5]
M4[5]
I
TMS — Test Mode Select for JTAG interface.
TRST — Test Reset for JTAG interface.
P1.31/TRST
P2.0 to P2.31
I
I/O
Port 2 — Port 2 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 2 pins
depends upon the pin function selected via the Pin Connect
Block.
P2.0/D0
98[5]
E12[5]
C12[5]
C11[5]
B12[5]
A13[5]
C10[5]
B10[5]
A10[5]
D9[5]
C9[5]
A9[5]
A8[5]
B7[5]
C7[5]
A6[5]
B6[5]
C6[5]
D6[5]
A5[5]
B5[5]
D5[5]
A4[5]
A1[5]
E3[5]
E2[5]
E1[5]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D0 — External memory data line 0.
D1 — External memory data line 1.
D2 — External memory data line 2.
D3 — External memory data line 3.
D4 — External memory data line 4.
D5 — External memory data line 5.
D6 — External memory data line 6.
D7 — External memory data line 7.
D8 — External memory data line 8.
D9 — External memory data line 9.
D10 — External memory data line 10.
D11 — External memory data line 11.
D12 — External memory data line 12.
D13 — External memory data line 13.
D14 — External memory data line 14.
D15 — External memory data line 15.
D16 — External memory data line 16.
D17 — External memory data line 17.
D18 — External memory data line 18.
D19 — External memory data line 19.
D20 — External memory data line 20.
D21 — External memory data line 21.
D22 — External memory data line 22.
D23 — External memory data line 23.
D24 — External memory data line 24.
D25 — External memory data line 25.
P2.1/D1
105[5]
106[5]
108[5]
109[5]
114[5]
115[5]
116[5]
117[5]
118[5]
120[5]
124[5]
125[5]
127[5]
129[5]
130[5]
131[5]
132[5]
133[5]
134[5]
136[5]
137[5]
1[5]
P2.2/D2
P2.3/D3
P2.4/D4
P2.5/D5
P2.6/D6
P2.7/D7
P2.8/D8
P2.9/D9
P2.10/D10
P2.11/D11
P2.12/D12
P2.13/D13
P2.14/D14
P2.15/D15
P2.16/D16
P2.17/D17
P2.18/D18
P2.19/D19
P2.20/D20
P2.21/D21
P2.22/D22
P2.23/D23
P2.24/D24
P2.25/D25
10[5]
11[5]
12[5]
LPC2210_2220_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2008
11 of 50
NXP [ NXP ]
