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ISP1581BD,518 参数 Datasheet PDF下载

ISP1581BD,518图片预览
型号: ISP1581BD,518
PDF下载: 下载PDF文件 查看货源
内容描述: [IC UNIVERSAL SERIAL BUS CONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64, Bus Controller]
分类和应用: 时钟数据传输外围集成电路
文件页数/大小: 80 页 / 389 K
品牌: NXP [ NXP ]
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ISP1581  
Hi-Speed USB peripheral controller  
Philips Semiconductors  
6.2 Pin description  
Table 2:  
Symbol[1]  
DGND  
Pin description for LQFP64  
Pin  
1
Type[2] Description  
-
-
digital ground  
[3]  
VCC(5.0)  
2
supply voltage (3.3 or 5.0 V)  
for 5.0 V operation, this is the only pin used. Refer to  
Section 10  
AGND  
3
4
-
-
analog ground  
[3]  
VCCA(3.3)  
regulated supply voltage (3.3 V ± 0.3 V) from internal  
regulator; supplies internal analog circuits; used to connect  
decoupling capacitor and 1.5 kpull-up resistor on D+ line  
Remark: Cannot be used to supply external devices. Refer  
to Section 10  
D−  
5
6
7
A
A
A
USB Dconnection (analog)  
USB D+ connection (analog)  
D+  
RPU  
connection for external pull-up resistor for USB D+ line;  
must be connected to VCCA(3.3) via a 1.5 kresistor  
RREF  
8
9
A
I
connection for external bias resistor; must be connected to  
ground via a 12.0 k(± 1%) resistor  
MODE1  
selects function of pin ALE/A0 (in Split Bus mode only):  
0 — ALE function (address latch enable)  
1 — A0 function (address/data indicator).  
Remark: Connect to VCC(5.0) in the Generic Processor  
mode.  
input pad; TTL; 5 V tolerant; internal pull-down resistor.  
RESET  
EOT  
10  
11  
I
I
reset input; a LOW level produces an asynchronous reset;  
connect to VCC for power-on reset (internal POR circuit)  
TTL with hysteresis; 5 V tolerant; internal pull-up resistor.  
End Of Transfer input (programmable polarity, see  
Table 37); used in DMA slave mode only; when not in use,  
connect this pin to VCC(I/O) through a 10 kresistor  
input pad; TTL; 5 V tolerant; 5 ns slew rate control.  
DREQ  
DACK  
12  
13  
I/O  
I/O  
DMA request (programmable polarity); direction depends  
on the bit MASTER in the DMA Hardware register (DMA  
master: input, DMA slave: output); see Table 35 and  
Table 36; when not in use, connect this pin to ground  
through a 10 kresistor;  
bidirectional pad; push pull output; 5 ns slew rate control;  
TTL; 5 V tolerant.  
DMA acknowledge (programmable polarity); direction  
depends on bit MASTER in the DMA Hardware register  
(DMA slave: input, DMA master: output); see Table 35 and  
Table 36; when not in use, connect this pin to VCC(I/O)  
through a 10 kresistor  
bidirectional pad; push pull output; 5 ns slew rate control;  
TTL; 5 V tolerant.  
9397 750 13462  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 06 — 23 December 2004  
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