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DREQ, DACK,
DIOR, DIOW
CS0, CS1,
to/from USB
12 MHz
DA0 , DA1 , DA2
*
*
D+
D−
5
4
XTAL1
60
XTAL2
59
6
5
18, 17,
19, 20, 21
12, 13,
14, 15
11
16
22
EOT
3.3 V
DMA
HANDLER
INTRQ
DMA
INTERFACE
IORDY
*
1.5
kΩ
40, 41,
SoftConnect
44 to 57 16
RPU
7
8
PHILIPS
SIE/PIE
DATA0 to DATA15
19
MEMORY
MANAGEMENT
UNIT
BUS_CONF
*
DMA
REGISTERS
20, 9
2
RREF
Hi-Speed USB
TRANSCEIVER
MODE0 , MODE1
*
12.0 kΩ
22
READY
*
MICRO
CONTROLLER
INTERFACE
30 to 35, 38, 39
8
4
INTEGRATED
RAM
(8 KBYTE)
MICRO-
CONTROLLER
HANDLER
AD0 to AD7
10
2
POWER-ON
RESET
internal
reset
RESET
25, 29, 26, 27
28
CS, ALE/A0, (R/W)/RD,
DS/WR
3.3 V
3.3 V
digital
supply
INT
VOLTAGE
REGULATORS
SYSTEM
CONTROLLER
V
CC(5.0)
analog
supply
5 V
ISP1581
1, 23,
36, 42, 61
24, 37,
43, 58, 64
3
4
63
62
004aaa153
5
1
5
Denotes shared pin usage
*
V
DGND AGND
TEST WAKEUP
CC(3.3)
V
CCA(3.3)
The direction of pins DREQ, DACK, DIOR and DIOW is determined by bit MASTER (DMA Hardware register) and bit ATA_MODE (DMA Configuration register).
Fig 1. Block diagram.
NXP [ NXP ]
