ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
14.1.2 Split Bus mode (BUS_CONF = 0)
Split Bus mode (BUS_CONF = 0, MODE1 = 0, MODE0 = 0/1)
T
cy(RW)
t
WHSH
CS
]
[
data
data
(read) AD 7:0
address
t
WHDZ
[
]
(write) AD 7:0
address
t
DVWH
t
t
LLWL
LLI2L
t
WLWH
DS
(I2)
t
I2HI1X
R/W
(I1)
t
t
AVLL
I1VLL
ALE
MGT498
Fig 14. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 0, MODE0 = 0).
T
cy(RW)
t
WHSH
CS
t
t
RLDV
RHDZ
[
]
data
(read) AD 7:0
address
t
t
t
LLRL
RLRH
RHSH
RD
t
WHDZ
[
]
(write) AD 7:0
data
address
t
t
DVWH
t
LLWL
t
LLI2L
WLWH
WR
(I2)
t
AVLL
ALE
004aaa132
Fig 15. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 0, MODE0 = 1).
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
55 of 79
NXP [ NXP ]
