ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
14.1 Register access timing
14.1.1 Generic Processor mode (BUS_CONF = 1)
T
cy(RW)
t
WHSH
t
RHSH
CS
t
WHAX
t
RHAX
[
]
AD 7:0
t
t
RLDV
RHDZ
[
]
(read) DATA 15:0
t
t
AVRL
RLRH
RD
t
WHDZ
t
AVWL
[
]
(write) DATA 15:0
t
t
I1VI2L
DVWH
t
WR
(I2)
WLWH
004aaa130
Fig 11. ISP1581 register access timing: separate address and data buses (MODE0 = 1).
T
cy(RW)
t
WHSH
t
RHSH
CS
t
WHAX
t
RHAX
[
]
AD 7:0
t
t
RLDV
RHDZ
[
]
(read) DATA 15:0
t
WHDZ
t
t
AVWL
I1VI2L
[
]
(write) DATA 15:0
t
DVWH
t
DS
(I2)
WLWH
t
I2HI1X
read
write
R/W
(I1)
004aaa131
Fig 12. ISP1581 register access timing: separate address and data buses (MODE0 = 0).
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
53 of 79
NXP [ NXP ]
