ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Table 139: DcChipID register: bit description
Bit
Symbol
Description
15 to 8
7 to 0
CHIPIDH[7:0]
CHIPIDL[7:0]
chip ID code (36H)
silicon version (30H, with 30 representing the BCD
encoded version number)
16.3.6 DcInterrupt register (R: C0H)
This command indicates the sources of interrupts as stored in the 4-byte DcInterrupt
register. Each individual endpoint has its own interrupt bit. The bit allocation of the
DcInterrupt register is shown in Table 140. Bit BUSTATUS is used to verify the current
bus status in the interrupt service routine. Interrupts are enabled using the
DcInterruptEnable register, see Section 16.1.5.
While reading the DcInterrupt register, it is recommended that both 2-byte words are
read completely.
Code (Hex): C0 — read DcInterrupt register
Transaction — read 4 bytes (code or data)
Table 140: DcInterrupt register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
21
EP12
0
-
-
-
23
22
20
EP11
0
19
EP10
0
18
17
16
Symbol
Reset
Access
Bit
EP14
EP13
EP9
EP8
EP7
0
0
0
0
0
R
R
R
R
R
R
R
R
15
14
13
EP4
0
12
EP3
0
11
EP2
0
10
9
8
Symbol
Reset
Access
Bit
EP6
EP5
EP1
EP0IN
EP0OUT
0
0
0
0
0
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
Symbol
Reset
Access
BUSTATUS
SP_EOT
PSOF
0
SOF
0
EOT
0
SUSPND
RESUME
RESET
0
0
0
0
0
R
R
R
R
R
R
R
R
Table 141: DcInterrupt register: bit description
Bit
Symbol
Description
31 to 24
-
reserved
23 to 10
EP14 to EP1 Logic 1 indicates the interrupt source(s): endpoint 14 to 1.
9
8
7
6
EP0IN
Logic 1 indicates the interrupt source: control IN endpoint.
Logic 1 indicates the interrupt source: control OUT endpoint.
Monitors the current USB bus status (0 = awake, 1 = suspend).
EP0OUT
BUSTATUS
SP_EOT
Logic 1 indicates that an EOT interrupt has occurred for a short
period.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
127 of 150
NXP [ NXP ]
