NXP Semiconductors
HEF4094B
8-stage shift-and-store register
6. Functional description
Table 3.
Inputs
CP
↑
↓
↑
↑
↑
↓
[1]
Function table
Parallel outputs
OE
L
L
H
H
H
H
STR
X
X
L
H
H
H
D
X
X
X
L
H
H
QP0
Z
Z
NC
L
H
NC
QPn
Z
Z
NC
QPn
−1
QPn
−1
NC
Serial outputs
QS1
Q6S
NC
Q6S
Q6S
Q6S
NC
QS2
NC
Q7S
NC
NC
NC
Q7S
At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
↑
= positive-going transition;
↓
= negative-going transition;
Z = HIGH-impedance OFF-state; NC = no change;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
OUTPUT QP0
INTERNAL Q6S (FF 6)
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
001aaf117
Z-state
Z-state
Fig 5.
Timing diagram
HEF4094B_8
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 2 April 2010
4 of 19
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