HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
Table 8.
Power dissipation
Dynamic power dissipation PD and total power dissipation Ptot can be calculated from the formulas shown. Tamb = 25 C.
Symbol Parameter
Conditions
VDD Typical formula for PD and Ptot (W)[1]
2
PD
dynamic power per device
dissipation
5 V PD = 700 fi + (fo CL) VDD
2
10 V PD = 3300 fi + (fo CL) VDD
2
15 V PD = 8900 fi + (fo CL) VDD
Ptot
total power
dissipation
when using
the on-chip
oscillator
5 V Ptot = 700 fosc + (fo CL) VDD2 + 2 Ct VDD2 fosc + 690 VDD
10 V Ptot = 3300 fosc + (fo CL) VDD2 + 2 Ct VDD2 fosc + 6900 VDD
15 V Ptot = 8900 fosc + (fo CL) VDD2 + 2 Ct VDD2 fosc + 22000 VDD
[1] Where:
fi = input frequency in MHz; fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
(fo CL) = sum of the outputs;
Ct = timing capacitance (pF);
fosc = oscillator frequency (MHz).
11. Waveforms
t
t
f
r
90 %
MR input
V
M
10 %
t
W
1/f
t
max
rec
V
RS input
M
t
W
t
t
t
PHL
PHL
PLH
90 %
Qn output
V
M
10 %
t
t
t
t
001aaj472
Measurement points are given in Table 9.
Fig 4. Waveforms showing propagation delays for MR to Qn and CP to Q0, minimum MR, and CP pulse widths
Table 9. Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
HEF4060B-Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 28 February 2013
6 of 14
NXP [ NXP ]
