HEF4060B-Q100
NXP Semiconductors
14-stage ripple-carry binary counter/divider and oscillator
5.2 Pin description
Table 2.
Symbol
Q11 to Q13
Q3 to Q9
VSS
Pin description
Pin
Description
1, 2, 3
counter output
7, 5, 4, 6, 14, 13, 15
counter output
8
ground supply voltage
external capacitor connection
oscillator pin
CEXT
REXT
RS
9
10
11
12
16
clock input/oscillator pin
master reset
MR
VDD
supply voltage
6. Functional description
Table 3.
Function table[1]
Input
RS
Output
MR
L
Q3 to Q9 and Q11 to Q13
no change
L
count
L
X
H
[1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH clock transition; HIGH-to-LOW clock transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
Max
+18
Unit
V
supply voltage
0.5
input clamping current
input voltage
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
-
10
mA
V
VI
0.5
VDD + 0.5
10
IOK
output clamping current
input/output current
supply current
-
mA
mA
mA
C
II/O
-
10
IDD
-
50
Tstg
Tamb
Ptot
P
storage temperature
ambient temperature
total power dissipation
power dissipation
65
+150
+85
40
C
[1]
Tamb 40 C to +85 C
-
-
500
mW
mW
per output
100
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
HEF4060B-Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 28 February 2013
3 of 14
NXP [ NXP ]
