NXP Semiconductors
HEF4053B-Q100
Triple single-pole double-throw analog switch
t
W
V
I
negative
pulse
0V
90 %
V
M
10 %
t
f
t
r
V
I
positive
pulse
0V
10 %
90 %
V
M
t
W
V
DD
V
DD
V
I
PULSE
GENERATOR
VI
VO
RL
S1
V
M
t
r
t
f
V
M
DUT
RT
CL
open
V
SS
V
EE
001aaj903
Test data is given in
Definitions:
DUT = Device Under Test.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= Load capacitance including test jig and probe.
R
L
= Load resistance.
Fig 15. Test circuit for measuring switching times
Table 10.
Input
nYn, nZ
Sn and E
t
r
, t
f
V
M
0.5V
DD
V
DD
or V
EE
V
DD
or V
SS
20 ns
[1]
Test data
Load
C
L
50 pF
R
L
10 k
S1 position
t
PHL[1]
t
PLH
t
PZH
, t
PHZ
t
PZL
, t
PLZ
other
V
EE
V
DD
V
EE
V
DD
or V
EE
V
EE
For nYn to nZ or nZ to nYn propagation delays use V
EE
. For Sn to nYn or nZ propagation delays use V
DD
.
HEF4053B_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 22 February 2013
10 of 19
PHILIPS [ NXP SEMICONDUCTORS ]
