74LVC74A
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
V
I
V
M
nCP input
GND
t
rec
V
I
V
M
nSD input
nRD input
GND
t
t
W
W
V
I
V
M
GND
t
t
PHL
PLH
V
OH
nQ output
nQ output
V
V
M
V
OL
V
OH
M
V
OL
t
t
PLH
mna423
PHL
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse
widths, and the nRD to nCP recovery time
Table 9.
Measurement points
Supply voltage
VCC
Input
VI
Output
VM
VM
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
0.5 VCC
0.5 VCC
0.5 VCC
1.5 V
0.5 VCC
0.5 VCC
0.5 VCC
1.5 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
1.5 V
1.5 V
74LVC74A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 20 November 2012
10 of 19
NXP [ NXP ]
