NXP Semiconductors
74LV08-Q100
Quad 2-input AND gate
11. Waveforms
V
I
nA, nB input
GND
t
PHL
V
OH
nY output
V
OL
V
M
mna224
V
M
t
PLH
Measurement points are given in
Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6.
Table 8.
V
CC
< 2.7 V
The input (nA, nB) to output (nY) propagation delays
Measurement points
Input
V
M
0.5V
CC
1.5 V
0.5V
CC
Output
V
M
0.5V
CC
1.5 V
0.5V
CC
Supply voltage
2.7 V to 3.6 V
4.5 V
V
CC
PULSE
GENERATOR
V
I
DUT
RT
CL
50 pF
RL
1 kΩ
V
O
001aaa663
Test data is given in
Table 9.
Definitions test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
Fig 7.
Table 9.
V
CC
< 2.7 V
Load circuit for switching times
Test data
Input
V
I
V
CC
2.7 V
V
CC
t
r
, t
f
2.5 ns
2.5 ns
2.5 ns
Supply voltage
2.7 V to 3.6 V
4.5 V
74LV08_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 31 July 2012
6 of 12
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