NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics
…continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see
Figure 12
Symbol Parameter
C
PD
power
dissipation
capacitance
Conditions
Min
per package;
V
I
= GND to V
CC
−
1.5 V
25
°C
Typ Max
35
-
-
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
-
Max
-
Min
-
Max
-
pF
[1]
[2]
[3]
t
pd
is the same as t
PHL
and t
PLH
.
t
t
is the same as t
THL
and t
TLH
.
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V.
12. Waveforms
1/f
max
V
I
CP or CE input
GND
t
W
t
PHL
V
OH
Q7 or Q7 output
V
OL
t
THL
t
TLH
mna987
V
M
t
PLH
V
M
Measurement points are given in
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7.
The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the
maximum clock frequency and the output transition times
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
11 of 22
PHILIPS [ NXP SEMICONDUCTORS ]
