Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT107
Fig.4 Functional diagram.
Fig.5 Logic diagram (one flip-flop).
FUNCTION TABLE
INPUTS
OPERATING MODE
nR
asynchronous reset
toggle
load “0” (reset)
load “1” (set)
hold “no change”
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP
transition
X = don’t care
↓
= HIGH-to-LOW CP transition
L
H
H
H
H
X
↓
↓
↓
↓
nCP
X
h
I
h
I
J
X
h
h
I
I
K
L
q
L
H
q
Q
H
q
H
L
q
Q
OUTPUTS
December 1990
4
PHILIPS [ NXP SEMICONDUCTORS ]
