NXP Semiconductors
74HC08-Q100; 74HCT08-Q100
Quad 2-input AND gate
4. Functional diagram
1
2
&
3
4
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
5
&
6
2Y
6
9
10
&
8
3Y
8
A
12
13
B
&
4Y
11
11
Y
mna222
mna223
mna221
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
+&4
+&74
$
%
<
$
%
<
*1'
DDD
+&4
+&74
9
&&
%
$
<
%
$
<
WHUPLQDO
LQGH[ DUHD
%
<
$
%
<
*1'
9
&&
%
$
<
%
$
*1'
$
<
DDD
7UDQVSDUHQW WRS YLHZ
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4.
Pin configuration DIP14, SO14 and (T)SSOP14
Fig 5.
Pin configuration DHVQFN14
74HC_HCT08_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 16 July 2012
2 of 14
PHILIPS [ NXP SEMICONDUCTORS ]
