74HC74DB118 参数 Datasheet PDF下载

NXP Semiconductors

74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

6. Functional description

Table 3.

Input

nSD

L

H

L

[1]

Function table

Output

nRD

H

L

L

nCP

X

X

X

nD

X

X

X

nQ

H

L

H

nQ

L

H

H

H = HIGH voltage level; L = LOW voltage level; X = don’t care.

Table 4.

Input

nSD

H

H

[1]

Function table

Output

nRD

H

H

nCP





nD

L

H

nQ

n+1

L

H

nQ

n+1

H

L

H = HIGH voltage level; L = LOW voltage level;



= LOW-to-HIGH transition; Q

n+1

= state after the next LOW-to-HIGH CP transition;

X = don’t care.

7. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V

CC

I

IK

I

OK

I

O

I

CC

I

GND

T

stg

P

tot

Parameter

supply voltage

input clamping current

output clamping current

output current

supply current

ground current

storage temperature

total power dissipation

DIP14 package

SO14, (T)SSOP14 and DHVQFN14

packages

[1]

For DIP14 package: P

tot

derates linearly with 12 mW/K above 70

C.

For SO14 package: P

tot

derates linearly with 8 mW/K above 70

C.

For (T)SSOP14 packages: P

tot

derates linearly with 5.5 mW/K above 60

C.

For DHVQFN14 packages: P

tot

derates linearly with 4.5 mW/K above 60

C.

Conditions

V

I

<

0.5

V or V

I

> V

CC

+ 0.5 V

V

O

<

0.5

V or V

O

> V

CC

+ 0.5 V

V

O

=

0.5

V to (V

CC

+ 0.5 V)

Min

0.5

-

-

-

-

100

65

-

-

Max

+7

20

20

25

+100

-

+150

750

500

Unit

V

mA

mA

mA

mA

mA

C

mW

mW

74HC_HCT74

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 4 — 27 August 2012

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