NXP Semiconductors
74HC4052-Q100; 74HCT4052-Q100
Dual 4-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
74HC4052-Q100
74HCT4052-Q100
2Y0
2Y2
2Z
2Y3
2Y1
E
V
EE
GND
1
2
3
4
5
6
7
8
aaa-003162
74HC4052-Q100
74HCT4052-Q100
terminal 1
index area
2Y2
2
3
4
5
6
7
8
GND
S1
9
V
CC(1)
16 V
CC
15 1Y2
14 1Y1
13 1Z
12 1Y0
11 1Y3
10 S0
2Y0
1
2Z
2Y3
2Y1
E
V
EE
16 V
CC
15 1Y2
14 1Y1
13 1Z
12 1Y0
11 1Y3
10 S0
9
S1
aaa-003163
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 5.
Pin configuration for SO16 and TSSOP16
Fig 6.
Pin configuration for DHVQFN16
6.2 Pin description
Table 2.
Symbol
2Y0, 2Y1, 2Y2, 2Y3
1Z, 2Z
E
V
EE
GND
S0, S1
1Y0, 1Y1, 1Y2, 1Y3
V
CC
Pin description
Pin
1, 5, 2, 4
13, 3
6
7
8
10, 9
12, 14, 15, 11
16
Description
independent input or output
common input or output
enable input (active LOW)
negative supply voltage
ground (0 V)
select logic input
independent input or output
positive supply voltage
74HC_HCT4052_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 22 November 2012
4 of 26
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