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74HC4017 参数 Datasheet PDF下载

74HC4017图片预览
型号: 74HC4017
PDF下载: 下载PDF文件 查看货源
内容描述: 10解码输出约翰逊十进制计数器 [Johnson decade counter with 10 decoded outputs]
分类和应用: 计数器
文件页数/大小: 12 页 / 90 K
品牌: NXP [ NXP ]
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Philips Semiconductors  
Product specification  
Johnson decade counter with 10 decoded outputs  
74HC/HCT4017  
CP1) and an overriding asynchronous master reset input  
(MR).  
FEATURES  
Output capability: standard  
ICC category: MSI  
The counter is advanced by either a LOW-to-HIGH  
transition at CP0 while CP1 is LOW or a HIGH-to-LOW  
transition at CP1 while CP0 is HIGH (see also function  
table).  
GENERAL DESCRIPTION  
The 74HC/HCT4017 are high-speed Si-gate CMOS  
devices and are pin compatible with the “4017” of the  
“4000B” series. They are specified in compliance with  
JEDEC standard no. 7A.  
When cascading counters, the Q5-9 output, which is LOW  
while the counter is in states 5, 6, 7, 8 and 9, can be used  
to drive the CP0 input of the next counter.  
A HIGH on MR resets the counter to zero  
(Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the  
clock inputs (CP0 and CP1).  
The 74HC/HCT4017 are 5-stage Johnson decade  
counters with 10 decoded active HIGH outputs (Q0 to Q9),  
an active LOW output from the most significant flip-flop  
(Q5-9), active HIGH and active LOW clock inputs (CP0 and  
Automatic code correction of the counter is provided by an  
internal circuit: following any illegal code the counter  
returns to a proper counting mode within 11 clock pulses.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
PARAMETER  
CONDITIONS  
UNIT  
ns  
HC  
HCT  
21  
tPHL/ tPLH  
fmax  
propagation delay CP0, CP1 to Qn  
maximum clock frequency  
CL = 15 pF; VCC = 5 V 20  
77  
67  
3.5  
36  
MHz  
pF  
CI  
input capacitance  
3.5  
35  
CPD  
power dissipation capacitance per package  
notes 1 and 2  
pF  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
PD = CPD × VCC2 × fi+(CL × VCC2 × fo) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
(CL × VCC2 × fo) = sum of outputs  
CL = output load capacitance in pF  
VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC 1.5 V  
ORDERING INFORMATION  
See “74HC/HCT/HCU/HCMOS Logic Package Information”.  
December 1990  
2
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