74HC273D 参数 Datasheet PDF下载

NXP Semiconductors

74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

6. Functional description

Table 3.

Function table

Inputs

MR

reset (clear)

load “1”

load “0”

[1]

H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care;



= LOW-to-HIGH clock transition.

Operating modes

Outputs

CP

X





Dn

X

h

l

Qn

L

H

L

L

H

H

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)

Symbol

V

CC

I

IK

I

OK

I

O

I

CC

I

GND

T

stg

P

tot

Parameter

supply voltage

input clamping current

output clamping current

output current

supply current

ground current

storage temperature

total power dissipation

T

amb

=

40 C

to +125

C

DIP20 package

SO20, SSOP20, TSSOP20 and

DHVQFN20 package

[1]

[2]

[3]

Conditions

V

I

<

0.5

V or V

I

> V

CC

+ 0.5 V

V

O

<

0.5

V or V

O

> V

CC

+ 0.5 V

0.5

V < V

O

< V

CC

+ 0.5 V

Min

0.5

-

-

-

-

50

65

-

-

Max

+7

20

20

25

50

-

+150

750

500

Unit

V

mA

mA

mA

mA

mA

C

mW

mW

The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

For DIP20 package: above 70

C

the value of P

tot

derates linearly with 12 mW/K.

For SO20 package: above 70

C

the value of P

tot

derates linearly with 8 mW/K.

For SSOP20 and TSSOP20 packages: above 60

C

the value of P

tot

derates linearly with 5.5 mW/K.

For DHVQFN20 packages: P

tot

derates linearly with 4.5 mW/K above 60

C.

74HC_HCT273

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 4 — 10 June 2013

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