74HC166-Q100; 74HCT166-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
6. Functional description
Table 3.
Function table[1]
Operating modes
Inputs
Qn registers
Output
PE
I
CE
CP
DS
X
X
l
D0 to D7
Q0
L
Q1 to Q6 Q7
parallel load
I
I
L to L
L
I
I
h
X
X
X
H
H to H
H
serial shift
h
I
L
q0 to q5
q0 to q5
q1 to q6
q6
q6
q7
h
I
h
H
hold “do nothing”
X
H
X
X
q0
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
CP
mode
control
inputs
CE
MR
DS
shift/
load
D0
D1
D2
D3
D4
D5
D6
H
L
H
L
parallel
inputs
H
L
H
H
D7
Q7
output
L
L
L
H
H
H
H
H
serial shift
serial shift
inhibit
clear
load
aaa-008820
Fig 6. Typical clear, shift, load, inhibit, and shift sequences
74HC_HCT166_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 25 September 2013
5 of 19
NXP [ NXP ]
