74HC166-Q100; 74HCT166-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
5. Pinning information
5.1 Pinning
ꢀꢁ+&ꢂꢃꢃꢄ4ꢂꢅꢅ
ꢀꢁ+&7ꢂꢃꢃꢄ4ꢂꢅꢅ
ꢁ
ꢃ
ꢄ
ꢇ
ꢆ
ꢅ
ꢂ
ꢈ
ꢁꢅ
ꢁꢆ
ꢁꢇ
ꢁꢄ
ꢁꢃ
ꢁꢁ
ꢁꢀ
ꢉ
'6
'ꢀ
9
&&
3(
'ꢂ
4ꢂ
'ꢅ
'ꢆ
'ꢇ
05
'ꢁ
'ꢃ
'ꢄ
&(
&3
*1'
DDDꢀꢁꢁꢂꢃꢂꢄ
Fig 5. Pin configuration (SO16 and TSSOP16)
5.2 Pin description
Table 2.
Symbol
DS
Pin description
Pin
Description
1
serial data input
D0 to D7
CE
2, 3, 4, 5, 10, 11, 12, 14
parallel data inputs
6
clock enable input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
ground (0 V)
CP
7
GND
MR
8
9
asynchronous master reset (active LOW)
serial output from the last stage
parallel enable input (active LOW)
positive supply voltage
Q7
13
15
16
PE
VCC
74HC_HCT166_Q100
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Product data sheet
Rev. 1 — 25 September 2013
4 of 19
NXP [ NXP ]
