NXP Semiconductors
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
6.2 Pin description
Table 2.
Symbol
PL
CP
Q7
GND
Q7
DS
D0 to D7
CE
V
CC
Pin description
Pin
1
2
7
8
9
10
11, 12, 13, 14, 3, 4, 5, 6
15
16
Description
asynchronous parallel load input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
complementary output from the last stage
ground (0 V)
serial output from the last stage
serial data input
parallel data inputs (also referred to as Dn)
clock enable input (active LOW)
positive supply voltage
7. Functional description
Table 3.
Function table
Inputs
PL
parallel load
serial shift
L
L
H
H
H
H
hold “do nothing”
H
H
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Operating modes
Qn registers
CE
X
X
L
L
H
X
CP
X
X
L
L
X
H
DS
X
X
l
h
l
h
X
X
D0 to D7 Q0
L
H
X
X
X
X
X
X
L
H
L
H
L
H
q0
q0
L to L
H to H
q0 to q5
q0 to q5
q0 to q5
q0 to q5
q1 to q6
q1 to q6
Outputs
Q7
H
L
q6
q6
q6
q6
q7
q7
L
H
q6
q6
q6
q6
q7
q7
Q1 to Q6 Q7
74HC_HCT165_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
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