NXP Semiconductors
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
V
I
PL input
GND
t
W
V
I
CE, CP input
GND
t
PHL
V
OH
Q7 or Q7 output
V
OL
V
M
mna988
V
M
t
rec
V
M
Measurement points are given in
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8.
Parallel load (PL) pulse width, parallel load to output (Q7 or Q7) propagation delays, parallel load to clock
(CP) and clock enable (CE) recovery time
V
I
D7 input
GND
t
PLH
V
OH
Q7 output
V
OL
t
PHL
V
OH
Q7 output
V
OL
V
M
mna989
V
M
t
PHL
V
M
t
PLH
Measurement points are given in
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 9.
Data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW
74HC_HCT165_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
12 of 21
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