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74HC164PW 参数 Datasheet PDF下载

74HC164PW图片预览
型号: 74HC164PW
PDF下载: 下载PDF文件 查看货源
内容描述: 8位串行输入,并行输出移位寄存器 [8-bit serial-in, parallel-out shift register]
分类和应用: 移位寄存器
文件页数/大小: 24 页 / 128 K
品牌: NXP [ NXP ]
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74HC164; 74HCT164  
8-bit serial-in, parallel-out shift register  
Rev. 03 — 4 April 2005  
Product data sheet  
1. General description  
The 74HC164; 74HCT164 are high-speed Si-gate CMOS devices and are pin compatible  
with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
The 74HC164; 74HCT164 are 8-bit edge-triggered shift registers with serial data entry  
and an output from each of the eight stages. Data is entered serially through one of two  
inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry  
through the other input. Both inputs must be connected together or an unused input must  
be tied HIGH.  
Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input  
and enters into Q0, which is the logical AND of the two data inputs (DSA and DSB) that  
existed one set-up time prior to the rising clock edge.  
A LOW level on the master reset (MR) input overrides all other inputs and clears the  
register asynchronously, forcing all outputs LOW.  
2. Features  
Gated serial data inputs  
Asynchronous master reset  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C.  
3. Quick reference data  
Table 1:  
Quick reference data  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Type 74HC164  
tPHL, tPLH  
propagation delay  
CP to Qn  
CL = 15 pF;  
-
-
12  
11  
-
-
ns  
ns  
V
CC = 5 V  
CL = 15 pF;  
CC = 5 V  
MR to Qn  
V
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