NXP Semiconductors
74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
A2
Y7
Y6
A1
Y5
A0
Y4
E1
Y3
E2
Y2
E3
Y1
Y0
001aae059
Fig 3.
Logic diagram
5. Pinning information
5.1 Pinning
74HC138/Q100
74HCT138/Q100
74HC138/Q100
74HCT138/Q100
A0
A1
A2
E1
E2
E3
Y7
GND
1
2
3
4
5
6
7
8
aaa-003153
terminal 1
index area
A1
2
3
4
5
6
7
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
Y6
9
aaa-003154
© NXP B.V. 2012. All rights reserved.
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9
Y6
A2
E1
E2
E3
Y7
GND
(1)
8
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 4.
Pin configuration SO16 and TSSOP16
Fig 5.
Pin configuration DHVQFN16
74HC_HCT138_Q100
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 1 — 16 July 2012
GND
1
A0
3 of 18
PHILIPS [ NXP SEMICONDUCTORS ]
