NXP Semiconductors
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
A2
Y7
Y6
A1
Y5
A0
Y4
E1
Y3
E2
Y2
E3
Y1
Y0
001aae059
Fig 3.
Logic diagram
5. Pinning information
5.1 Pinning
74HC138BQ
74HCT138BQ
terminal 1
index area
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
GND
Y6
10 Y5
9
001aae061
A0
A1
A2
E1
E2
E3
Y7
GND
1
2
3
4
5
6
7
8
A1
A2
E1
E2
E3
Y7
2
3
4
5
6
7
8
9
GND
(1)
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
1
A0
74HC138
74HCT138
001aae060
Y6
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 4.
Pin configuration DIP16, SO16, SSOP16 and
TSSOP16
Fig 5.
Pin configuration DHVQFN16
74HC_HCT138
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 June 2012
3 of 19
PHILIPS [ NXP SEMICONDUCTORS ]
