74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
4. Functional diagram
1
2
&
&
&
12
6
1
2
1A
1B
1C
2A
2B
2C
3A
3B
3C
13
1Y
2Y
12
6
13
3
3
4
5
4
5
A
9
9
10
11
3Y
8
10
11
Y
8
B
C
mna794
mna793
mna792
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram for one gate
5. Pinning information
5.1 Pinning
74HC11
74 HCT11
74HC11
74HCT11
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
1C
1Y
3C
3B
3A
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
2A
1C
1Y
3C
3B
3A
3Y
2A
2B
2B
2C
2C
2Y
2Y
8
GND
8
GND
001aal407
001aal408
Fig 4. Pin configuration DIP14 and SO14
Fig 5. Pin configuration (T)SSOP14
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A
1B, 2B, 3B
GND
Pin description
Pin
Description
data input
1, 3, 9
2, 4, 10
7
data input
ground (0 V)
data input
1C, 2C, 3C
1Y, 2Y, 3Y
VCC
13, 5, 11
12, 6, 8
14
data output
supply voltage
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
2 of 15
NXP [ NXP ]
