NXP Semiconductors
74HC04; 74HCT04
Hex inverter
4. Functional diagram
1
1
2
1
1A
1Y
2
3
1
4
3
2A
2Y
4
5
1
6
5
3A
3Y
6
9
1
8
9
4A
4Y
8
11
5A
5Y
10
11
1
10
13
6A
6Y
12
13
1
mna343
12
A
Y
mna341
mna342
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one
inverter)
5. Pinning information
14 V
CC
13 6A
12 6Y
11 5A
10 5Y
9
7
GND
4Y
8
4A
terminal 1
index area
1Y
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
001aac441
2
3
4
5
6
14 V
CC
13 6A
12 6Y
2A
2Y
3A
3Y
04
11 5A
10 5Y
9
8
4A
4Y
GND
(1)
1
1A
04
001aac442
Transparent top view
(1) The die substrate is attached to the exposed die pad
using conductive die attach material. It cannot be used
as a supply pin or input.
Fig 4.
Pin configuration DIP14, SO14 and (T)SSOP14
Fig 5.
Pin configuration DHVQFN14
74HC_HCT04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 3 August 2012
2 of 17
PHILIPS [ NXP SEMICONDUCTORS ]
