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74HC00DB 参数 Datasheet PDF下载

74HC00DB图片预览
型号: 74HC00DB
PDF下载: 下载PDF文件 查看货源
内容描述: 四路2输入与非门 [Quad 2-input NAND gate]
分类和应用: 栅极触发器逻辑集成电路光电二极管
文件页数/大小: 16 页 / 130 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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NXP Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Table 2.
Symbol
1Y to 4Y
GND
V
CC
Pin description
…continued
Pin
3, 6, 8, 11
7
14
Description
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
X
H
[1]
Function table
Output
nB
X
L
H
nY
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP14 package
SO14, (T)SSOP14 and
DHVQFN14 packages
[1]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
50
65
-
-
Max
+7
20
20
25
50
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For DIP14 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
74HC_HCT00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 14 December 2011
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