PI5A4684
Chip Scale Packaging,
Dual SPDT Analog Switch
Test Circuits and Timing Diagrams
V
CC
V
CC
NC
COM
V
N
V
OUT
or NO
R
C
35pF
L
L
50Ω
IN
GND
LOGIC
INPUT
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
Figure 1. AC Test Circuit
Notes:
1. Unused input (NC or NO) must be grounded.
VIH
t
t
r < 5ns
f < 5ns
Logic
Input
50%
Off
On
Off
tOFF
VIL
VOUT
Switch
Output 0V
90%
90%
tON
Logic Input Waveforms inverted for
Switches that have opposite logic
* 1.5V for 3.3V Supply
Figure 2. AC Waveforms
NC
NO
V
IN
50%
COM
Logic
Input
V
OUT
R
50Ω
C
L
35pF
L
V
OUT
IN
0.9 x V
OUT
Logic
Input
t
BBM
Figure 3. Break Before Make Interval Timing
5
PS8792B
05/09/06
06-0062
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
