PE3501
Product Specification
It is the responsibility of the customer to determine
proper supply decoupling for their design application.
Evaluation Kit
Evaluation Kit Operation
The DEC pin (3) must be connected to a low
impedance AC ground for proper device operation. On
the board, two decoupling capacitors (C6 = 10 nF,
C4 = 10 pF), located on the back of the board, perform
this function.
The TSSOP Prescaler Evaluation Board was designed
to help customers evaluate the PE3501 Divide-by-2
Prescaler. On this board, the device input (pin 2) is
connected to connector J1 through a 50 ꢀ transmission
line. A series capacitor (C1) provides the necessary
DC block for the device input. It is important to note
that the value of this capacitance will impact the
performance of the device. A value of 15 pF was found
to be optimal for this board layout; other applications
may require a different value.
Applications Support
If you have a problem with your evaluation kit or if
you have applications questions, please contact
applications support:
The device output (pin 7) is connected to connector J3
through a 50 ꢀ transmission line. A series capacitor
(C2) provides the necessary DC block for the device
output. Note that this capacitor must be chosen to
have a low impedance at the desired output frequency
the device. The value of 47 pF was chosen to provide
a wide operating range for the evaluation board.
E-Mail: help@psemi.com (fastest response)
Phone: (858) 731-9400
Figure 10. Evaluation Board Layouts
Peregrine Specification 101/0035
The board is constructed of a two-layer FR4 material
with a total thickness of 0.031”. The bottom layer
provides ground for the RF transmission lines. The
transmission lines were designed using a coplanar
waveguide above ground plane model with trace width
of 0.030”, trace gaps of 0.007”, dielectric thickness of
0.028”, metal thickness of 0.0014” and εr of 4.4. Note
that the predominate mode for these transmission lines
is coplanar waveguide.
J2 provides DC power to the device. Starting from the
lower left pin, the second pin to the right (J2-3) is
connected to the device VDD pin (1). Two decoupling
capacitors (10 pF, 1000 pF) are included on this trace.
Figure 11. Evaluation Board Schematic
Peregrine Specification 102/0013
©2005-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0111-04 │ UltraCMOS™ RFIC Solutions
Page 6 of 8
PSEMI [ Peregrine Semiconductor ]
