PE3501
Product Specification
Figure 3. Pin Configuration (Top View)
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
1
2
3
4
8
7
6
5
VDD
GND
FOUT
NC
FIN
3501
DEC
GND
Latch-Up Avoidance
GND
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 2. Pin Descriptions
Device Functional Considerations
Pin
No.
Pin
Name
Description
The PE3501 divides a 400 MHz to 3500 MHz
input signal by two, producing a 200 MHz to 1750
MHz output signal. To work properly, pin 3 must
be supplied with a bypass capacitor to ground. In
addition, the input and output signals (pins 2 & 7)
must be AC coupled via an external capacitor, as
shown in the test circuit in Figure 4.
1
2
VDD
Fin
Power supply pin. Bypassing is required.
Input signal pin. DC blocking capacitor
required (15 pF typical)
Power supply decoupling pin. Place a ca-
pacitor as close as possible and connect
directly to the ground plane.
3
4
DEC
GND
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 11 for a layout example.
5
6
7
8
GND
NC
Ground pin.
No Connection. This pin should be left
open.
Divided frequency output pin. DC blocking
capacitor required (47 pF typical)
Fout
GND
Ground pin.
Table 3. Absolute Maximum Ratings
Symbol
VDD
Parameter/Conditions Min Max Units
Supply voltage
4.0
15
V
dBm
°C
Pin
Input Power
TST
Storage temperature range
-65
-40
150
85
Operating temperature
range
TOP
°C
ESD voltage (Human Body
Model)
VESD
250
V
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
©2005-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0111-04 │ UltraCMOS™ RFIC Solutions
Page 2 of 8
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