PE3238
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Note 1:
Note 2:
Pin Name
f
p
V
DD
-f
p
Dout
V
DD
Cext
V
DD
PD_D
PD_U
V
DD
-f
c
f
c
GND
GND
f
r
LD
Enh
Interface Mode
ALL
ALL
Serial, Parallel
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
Serial, Parallel
Type
Output
(Note 2)
Output
(Note 1)
Output
(Note 1)
Output
Description
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
DD
pin 31.
V
DD
for f
p
.
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
Same as pin 1.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kohm series
resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
Same as pin 1.
PD_D is pulse down when f
p
leads f
c
.
PD_U is pulse down when f
c
leads f
p
.
(Note 2)
Output
V
DD
for f
c
.
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
DD
pin 38.
Ground.
Ground.
Input
Output,
OD
Input
Reference frequency input.
Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
V
DD
pins 1, 11, 12, 23, 31, 33, 35 and 38 are connected by diodes and must be supplied with the same positive voltage level.
V
DD
pins 31 and 38 are used to power the f
p
and f
c
outputs and can alternatively be left floating or connected to GND to disable the f
p
and f
c
outputs.
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 15
Document No. 70-0031-03
│
UltraCMOS™ RFIC Solutions
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