PE9702
Advance Information
Figure 2. Pin Configuration
GND
GND
GND
Enh
V
DD
LD
R
3
R
2
R
1
R
0
fr
6
D
0
, M
0
D
1
, M
1
D
2
, M
2
D
3
, M
3
V
DD
V
DD
S_WR, D
4
, M
4
Sdata, D
5
, M
5
Sclk, D
6
, M
6
FSELS, D
7
, Pre_en
GND
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
f
c
V
DD
_f
c
PD_U
PD_D
V
DD
C
ext
V
DD
D
out
V
DD
_f
p
f
p
GND
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
FSELP, A
0
E_WR, A
1
M2_WR, A
2
Smode, A
3
Bmode
V
DD
M1_WR
A_WR
Hop_WR
F
in
F
in
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
Pin Name
V
DD
R
0
R
1
R
2
R
3
GND
D
0
M
0
D
1
M
1
Interface Mode
ALL
Direct
Direct
Direct
Direct
ALL
Parallel
Direct
Parallel
Direct
Parallel
Direct
Parallel
Direct
ALL
ALL
Serial
Type
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended.
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
Parallel data bus bit2.
M Counter bit2.
Parallel data bus bit3.
M Counter bit3.
Same as pin 1.
Same as pin 1.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary
register data is transferred to the secondary register on S_WR or Hop_WR rising edge.
File No. 70/0036~00C
|
9
D
2
M
2
10
D
3
M
3
11
12
13
V
DD
V
DD
S_WR
Copyright
Peregrine Semiconductor Corp. 2003
UTSi
CMOS RFIC SOLUTIONS
Page 2 of 15
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