PE9702
Advance Information
Functional Description
The PE9702 consists of a prescaler, counters, a
phase detector, and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
Figure 3. Functional Block Diagram
R Counter
(6-bit)
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via serial bus,
parallel bus, or hardwired directly to the pins. There
are also various operational and test modes and a
lock detect output.
f
r
f
c
D(7:0)
Sdata
Control
Pins
Control
Logic
R(5:0)
M(8:0)
A(3:0)
Phase
Detector
PD_U
PD_D
LD
Cext
Modulus
Select
F
in
F
in
10/11
Prescaler
M Counter
(9-bit)
f
p
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0036~00C
|
UTSi
CMOS RFIC SOLUTIONS
Page 8 of 15
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