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4259-02 参数 Datasheet PDF下载

4259-02图片预览
型号: 4259-02
PDF下载: 下载PDF文件 查看货源
内容描述: SPDT大功率的UltraCMOS ? DC - 3.0 GHz射频开关 [SPDT High Power UltraCMOS⑩ DC - 3.0 GHz RF Switch]
分类和应用: 开关射频开关微波光电二极管
文件页数/大小: 8 页 / 180 K
品牌: PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
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PE4259
Product Specification
Figure 3. Pin Configuration (Top View)
pin 1
Table 4. DC Electrical Specifications
Parameter
Min
2.3
Typ
3.0
9
Max
3.3
20
Units
V
µA
V
RF1
GND
RF2
1
6
CTRL or V
DD
RFC
CTRL
V
DD
Power Supply
Voltage
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3V)
Control Voltage High
Control Voltage Low
259
2
5
3
4
0.7x V
DD
0.3x V
DD
V
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
Latch-Up Avoidance
Description
Pin
Name
RF1
GND
RF2
CTRL
RFC
RF Port1
3
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Figure 4. Maximum Input Power
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
RF Port2
3
Switch control input, CMOS logic level.
RF Common
3
This pin supports two interface options:
Single-pin control mode.
A nominal 3-volt
supply connection is required.
Complementary-pin control mode.
A
complementary CMOS control signal
to CTRL is supplied to this pin. By-
passing on this pin is not required in
this mode.
6
CTRL or
V
DD
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
ST
T
OP
P
IN
Parameter/Conditions
Power supply voltage
Voltage on any input
Storage temperature
range
Operating temperature
range
Input power (50Ω)
ESD Voltage (HBM,
ML_STD 883 Method
3015.7)
ESD Voltage (MM,
JEDEC, JESD22-A114-B)
Min
-0.3
-0.3
-65
-40
Max
4.0
V
DD
+
0.3
150
85
+34
4
2000
Units
V
V
°C
°C
dBm
V
V
ESD
250
Notes: 3. All RF pins must be DC blocked with an external series
capacitor or held at 0 V
DC
.
4. To maintain optimum device performance, do not exceed
Max P
IN
at desired operating frequency (see Figure 4).
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 8
Document No. 70-0134-02
UltraCMOS™ RFIC Solutions