PE3335
Product Specification
Main Counter Chain
Register Programming
The main counter chain divides the RF input
frequency, Fin, by an integer derived from the user
defined values in the “M” and “A” counters. It is
composed of the 10/11 dual modulus prescaler,
modulus select logic, and 9-bit M counter. Setting
Pre_en “low” enables the 10/11 prescaler. Setting
Pre_en “high” allows Fin to bypass the prescaler
and powers down the prescaler.
Parallel Interface Mode
Parallel Interface Mode is selected by setting the
Bmode input “low” and the Smode input “low”.
Parallel input data, D[7:0], are latched in a
parallel fashion into one of three, 8-bit primary
register sections on the rising edge of M1_WR,
M2_WR, or A_WR per the mapping shown in
Table 7 on page 10. The contents of the primary
register are transferred into a secondary register
on the rising edge of Hop_WR according to the
timing diagram shown in Figure 4. Data are
transferred to the counters as shown in Table 7
on page 10.
The output from the main counter chain, fp, is
related to the VCO frequency, Fin, by the following
equation:
fp = Fin / [10 x (M + 1) + A]
(1)
where A ≤ M + 1, 1 ≤ M ≤ 511
The secondary register acts as a buffer to allow
rapid changes to the VCO frequency. This
double buffering for “ping-pong” counter control
is programmed via the FSELP input. When
FSELP is “high”, the primary register contents
set the counter inputs. When FSELP is “low”, the
secondary register contents are utilized.
When the loop is locked, Fin is related to the
reference frequency, fr, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1))
(2)
where A ≤ M + 1, 1 ≤ M ≤ 511
A consequence of the upper limit on A is that Fin
must be greater than or equal to 90 x (fr / (R+1)) to
obtain contiguous channels. Programming the M
Counter with the minimum value of “1” will result in
a minimum M Counter divide ratio of “2”.
Parallel input data, D[7:0], are latched into the
enhancement register on the rising edge of
E_WR according to the timing diagram shown in
Figure 4. This data provides control bits as
shown in Table 8 on page 10 with bit
functionality enabled by asserting the Enh input
“low”.
When the prescaler is bypassed, the equation
becomes:
Fin = (M + 1) x (fr / (R+1))
(3)
where 1 ≤ M ≤ 511
Serial Interface Mode
Serial Interface Mode is selected by setting the
Bmode input “low” and the Smode input “high”.
In Direct Interface Mode, main counter inputs M7
and M8 are internally forced low.
While the E_WR input is “low” and the S_WR
input is “low”, serial input data (Sdata input), B0
to B19, are clocked serially into the primary
register on the rising edge of Sclk, MSB (B0)
first. The contents from the primary register are
transferred into the secondary register on the
rising edge of either S_WR or Hop_WR
according to the timing diagram shown in
Figures 4-5. Data are transferred to the counters
as shown in Table 7 on page 10.
Reference Counter
The reference counter chain divides the reference
frequency, fr, down to the phase detector
comparison frequency, fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
fc = fr / (R + 1)
(4)
The double buffering provided by the primary
and secondary registers allows for “ping-pong”
counter control using the FSELS input. When
FSELS is “high”, the primary register contents
set the counter inputs. When FSELS is “low”, the
secondary register contents are utilized.
where 0 ≤ R ≤ 63
Note that programming R equal to “0” will pass the
reference frequency, fr, directly to the phase
detector.
In Direct Interface Mode, R Counter inputs R4 and
R5 are internally forced low (“0”).
While the E_WR input is “high” and the S_WR
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions
Page 8 of 15
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