PE3335
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin No.
Pin
Name
Interface
Mode
Type
Description
(44-lead
PLCC)
(48-lead
QFN)
Prescaler complementary input. A bypass capacitor should be placed as
close as possible to this pin and be connected in series with a 50 Ω resistor
directly to the ground plane.
23
Fin
28
ALL
Input
29
30
31
32
33
24
25
26
27
28
GND
fp
ALL
ALL
ALL
Ground.
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
Output
(Note 1)
Output
(Note 1)
VDD-fp
Dout
VDD
VDD for fp. Can be left floating or connected to GND to disable the fp output.
Serial,
Parallel
Data Out. The MSEL signal and the raw prescaler output are available on
Dout through enhancement register programming.
ALL
ALL
Same as pin 1 (QFN48 pin 43).
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ
series resistor. Connecting Cext to an external capacitor will low pass filter
the input to the inverting amplifier used for driving LD.
34
29
Cext
Output
35
36
37
38
30
32
VDD
ALL
ALL
ALL
ALL
(Note 1)
Output
Same as pin 1 (QFN48 pin 43).
CP
Charge pump current is sourced when fc leads fp and sinked when fc lags fp.
No connection.
33, 34
35
NC
VDD-fc
(Note 1)
Output
VDD for fc can be left floating or connected to GND to disable the fc output.
Monitor pin for reference divider output. Switching activity can be disabled
through enhancement register programming or by floating or grounding VDD
pin 38.
39
36
fc
ALL
40
41
42
31,37
38,39
40
GND
GND
fr
ALL
ALL
ALL
Ground.
Ground.
Input
Reference frequency input.
Lock detect and open drain logical inversion of Cext. When the loop is in lock,
LD is high impedance, otherwise LD is a logic low (“0”).
43
44
41
LD
ALL
Output
Serial,
Parallel
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
42
Enh
Input
Note 1: All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
VDD-fp and VDD-fc are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp and fc
outputs.
Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions
Page 4 of 15
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