PE3335
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
(44-lead
PLCC)
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Note 1:
Pin No.
(48-lead
QFN)
23
24
25
26
27
28
29
30
32
33, 34
35
36
31,37
38,39
40
41
42
Pin
Name
Interface
Mode
Type
Description
Prescaler complementary input. A bypass capacitor should be placed as
close as possible to this pin and be connected in series with a 50
Ω
resistor
directly to the ground plane.
Ground.
F
in
GND
f
p
V
DD
-f
p
Dout
V
DD
Cext
V
DD
CP
NC
V
DD
-f
c
f
c
GND
GND
f
r
LD
Enh
ALL
ALL
ALL
ALL
Serial,
Parallel
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
Serial,
Parallel
Input
Output
(Note 1)
Output
(Note 1)
Output
(Note 1)
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
DD
pin 31.
V
DD
for f
p
. Can be left floating or connected to GND to disable the f
p
output.
Data Out. The MSEL signal and the raw prescaler output are available on
Dout through enhancement register programming.
Same as pin 1 (QFN48 pin 43).
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ
series resistor. Connecting Cext to an external capacitor will low pass filter
the input to the inverting amplifier used for driving LD.
Same as pin 1 (QFN48 pin 43).
Charge pump current is sourced when f
c
leads f
p
and sinked when f
c
lags f
p
.
No connection.
(Note 1)
Output
V
DD
for f
c
can be left floating or connected to GND to disable the f
c
output.
Monitor pin for reference divider output. Switching activity can be disabled
through enhancement register programming or by floating or grounding V
DD
pin 38.
Ground.
Ground.
Input
Output
Input
Reference frequency input.
Lock detect and open drain logical inversion of Cext. When the loop is in lock,
LD is high impedance, otherwise LD is a logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
All V
DD
pins are connected by diodes and must be supplied with the same positive voltage level.
V
DD
-f
p
and V
DD
-f
c
are used to power the f
p
and f
c
outputs and can alternatively be left floating or connected to GND to disable the f
p
and f
c
outputs.
Note 2:
All digital input pins have 70 kΩ pull-down resistors to ground.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 15
Document No. 70-0049-02
│
UltraCMOS™ RFIC Solutions
PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
