PE3335
Product Specification
input is “low”, serial input data (Sdata input), B
0
to
B
7
, are clocked serially into the enhancement
register on the rising edge of Sclk, MSB (B
0
) first.
The enhancement register is double buffered to
prevent inadvertent control changes during serial
loading, with buffer capture of the serially entered
data performed on the falling edge of E_WR
according to the timing diagram shown in Figure
5. After the falling edge of E_WR, the data provide
control bits as shown in Table 8 with bit
functionality enabled by asserting the
Enh
input
“low”.
Direct Interface Mode
Direct Interface Mode is selected by setting the
Bmode
input “high”.
Counter control bits are set directly at the pins as
shown in Table 7. In Direct Interface Mode, main
counter inputs M
7
and M
8
, and R Counter inputs
R
4
and R
5
are internally forced low (“0”).
Table 7. Primary Register Programming
Interface
Mode
Parallel
Enh
1
Bmode
0
Smode
0
R
5
R
4
M
8
M
7
Pre_en
M
6
M
5
M
4
M
3
M
2
M
1
M
0
R
3
R
2
R
1
R
0
A
3
A
2
A
1
A
0
M2_WR rising edge load
D
3
Serial*
Direct
1
1
0
1
1
X
B
0
0
D
2
B
1
0
D
1
B
2
0
D
0
B
3
0
D
7
B
4
Pre_en
D
6
B
5
M
6
M1_WR rising edge load
D
5
B
6
M
5
D
4
B
7
M
4
D
3
B
8
M
3
D
2
B
9
M
2
D
1
B
10
M
1
D
0
B
11
M
0
D
7
B
12
R
3
D
6
B
13
R
2
A_WR rising edge load
D
5
B
14
R
1
D
4
B
15
R
0
D
3
B
16
A
3
D
2
B
17
A
2
D
1
B
18
A
1
D
0
B
19
A
0
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Parallel
Serial*
Enh
0
0
Bmode
X
X
Smode
0
1
Reserved
D
7
B
0
Reserved
D
6
B
1
Reserved
D
5
B
2
Power
down
Counter
load
MSEL
output
D
2
B
5
Prescaler
output
D
1
B
6
f
c
, f
p
OE
D
0
B
7
E_WR rising edge load
D
4
D
3
B
3
B
4
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
Document No. 70-0049-02
│
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 15
PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
